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fuss:cpuflags [2014/02/06 13:34]
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fuss:cpuflags [2017/02/22 18:30] (current)
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 +====== Intel-defined CPU features, CPUID level 0x00000001 (ecx) ======
 +^ Flag ^ Description ^
 +|pni|Prescott New Instruction. This was the codename for SSE3 before it was released on the Intel Prescott processor (which was later added to the Pentium 4 family name).|
 +|pclmulqdq|PCLMULQDQ instruction (carry-less multiplication — accelerator for GCM)|
 +|dtes64|64-bit Debug Store|
 +|monitor/​mon|Monitor/​Mwait support (Intel SSE3 supplements)|
 +|ds_cpl|CPL Qual. Debug Store|
 +|vmx|Hardware virtualization:​ Intel VMX|
 +|smx|Safer mode: TXT (TPM support)|
 +|eist/​est|Enhanced SpeedStep|
 +|tm2|Thermal Monitor 2|
 +|sse3|Streaming SIMD Extensions 3. (An additional 13 instructions) introduced with "​Prescott"​ revision Intel Pentium 4 processors. AMD introduced SSE3 with the Athlon 64 "​Venice"​ revision|
 +|ssse3|Supplemental SSE-3|
 +|cid|Context ID|
 +|fma|Fused multiply-add|
 +|cx16|CMPXCHG16B. CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for high resolution counters that could be updated by multiple processors (or cores). Without CMPXCHG16B the only way to perform such an operation is by using a critical section.|
 +|xtpr|Send Task Priority Messages. TPR register chipset update control messenger. Part of the APIC code.|
 +|pdcm|Performance Capabilities|
 +|pcid|Process Context Identifiers|
 +|dca|Direct Cache Access|
 +|sse4|Streaming SIMD Extentions 4. Introduced with "​Nehalem"​ processor in 2008. Also known as "​Nehalem New Instructions (NNI)"​|
 +|sse4_1|Streaming SIMD Extentions 4.1|
 +|sse4_2|Streaming SIMD Extentions 4.2|
 +|x2apic|x2APIC|
 +|movbe|MOVBE instruction|
 +|popcnt|POPCNT instruction (Hamming weight, i.e. bit count)|
 +|tsc_deadline_timer|Tsc deadline timer|
 +|aes|AES instructions:​ AES-NI|
 +|xsave|XSAVE/​XRSTOR/​XSETBV/​XGETBV|
 +|avx|Advanced Vector Extensions|
 +|f16c|16-bit fp conversions (CVT16)|
 +|rdrand|The RDRAND instruction (hardware random number generator)|
 +|hypervisor|Running on a hypervisor|
 +
 +====== VIA/​Cyrix/​Centaur-defined CPU features, CPUID level 0xC0000001 ======
 +|rng|RNG present (xstore)|
 +|rng_en|RNG enabled|
 +|ace|on-CPU crypto (xcrypt)|
 +|ace_en|on-CPU crypto enabled|
 +|ace2|Advanced Cryptography Engine v2|
 +|ace2_en|ACE v2 enabled|
 +|phe|PadLock Hash Engine|
 +|phe_en|PHE enabled|
 +|pmm|PadLock Montgomery Multiplier|
 +|pmm_en|PMM enabled|
 +
 +====== Intel-defined CPU features, CPUID level 0x00000007:​0 (ebx) ======
 +^ Flag ^ Description ^
 +|fsgsbase|{RD/​WR}{FS/​GS}BASE instructions|
 +|bmi1|1st group bit manipulation extensions|
 +|hle|Hardware Lock Elision|
 +|avx2|AVX2 instructions|
 +|smep|Supervisor Mode Execution Protection|
 +|bmi2|2nd group bit manipulation extensions|
 +|erms|Enhanced REP MOVSB/​STOSB|
 +|invpcid|Invalidate Processor Context ID|
 +|rtm|Restricted Transactional Memory|
 +
 +====== Intel-defined CPU features, CPUID level 0x00000001 (edx) ======
 +^ Flag ^ Description ^
 +|fpu|Onboard FPU (floating point support)|
 +|vme|Virtual Mode Extensions (8086 mode)|
 +|de|Debugging Extensions (CR4.DE)|
 +|pse|Page Size Extensions (4MB pages)|
 +|tsc|Time Stamp Counter (RDTSC)|
 +|msr|Model-Specific Registers (RDMSR, WRMSR)|
 +|pae|Physical Address Extensions (support for more than 4GB of RAM). PAE is the added ability of the IA32 processor to address more than 4 GB of physical memory using Intel’s 36bit page addresses instead of the standard 32bit page addresses to access a total of 64GB of RAM. Also supported by many AMD chips.|
 +|mce|Machine Check Exception|
 +|cx8|CMPXCHG8 instruction (64-bit compare-and-swap). Compare and exchange 8 bytes. Also known as F00F, which is an abbreviation of the hexadecimal encoding of an instruction that exhibits a design flaw in the majority of older Intel Pentium CPU.|
 +|apic|Onboard APIC|
 +|sep|SYSENTER/​SYSEXIT|
 +|mtrr|Memory Type Range Registers|
 +|pge|Page Global Enable (global bit in PDEs and PTEs)|
 +|mca|Machine Check Architecture|
 +|cmov|CMOV instructions (conditional move) (also FCMOV)|
 +|pat|Page Attribute Table|
 +|pse36|36-bit PSEs (huge pages). Page Size Extensions 36. IA-32 supports two methods to access memory above 4 GB (32 bits), PSE and PAE. PSE is the older and far less used version.|
 +|pn|Processor serial number|
 +|clflush|CLFLUSH instruction|
 +|dts|Debug Store (buffer for debugging and profiling instructions),​ can also mean Digital Thermal Sensor.|
 +|acpi|ACPI via MSR (temperature monitoring and clock speed modulation)|
 +|mmxext/​mmx|Multimedia Extensions|
 +|fxsr|FXSAVE/​FXRSTOR,​ CR4.OSFXSR|
 +|sse|Streaming SIMD Extensions. Developed by Intel for its Pentium III but also implemented by AMD processors from Athlon XP onwards|
 +|sse2|Streaming SIMD Extensions 2. (An additional 144 SIMDs.) Introduced by Intel Pentium 4, on AMD since Athlon 64|
 +|ss|CPU self snoop|
 +|htt/​ht|Hyper-Threading or Hyper-Transport|
 +|tm|Automatic clock control (Thermal Monitor)|
 +|ia64|IA-64 processor (not to be confused with x86-64 = amd64, indicated by lm)|
 +|pbe|Pending Break Enable|
 +
 +====== AMD-defined CPU features, CPUID level 0x80000001 ======
 +^ Flag ^ Description ^
 +|syscall|SYSCALL/​SYSRET (calls between the operating system and the hardware).|
 +|mp|MP Capable.|
 +|nx|No eXecute, a flag that can be set on memory pages to disable execution of code in these pages.|
 +|mmxext|AMD MMX extensions|
 +|fxsr_opt|FXSAVE/​FXRSTOR optimizations|
 +|pdpe1gb|GB pages|
 +|rdtscp|RDTSCP|
 +|lm|Long Mode (x86-64: amd64, also known as Intel 64, i.e. 64-bit capable)|
 +|3dnowext|AMD 3DNow! extensions|
 +|3dnow|3DNow! (AMD vector instructions,​ competing with Intel'​s SSE1)|
 +
 +==== More extended AMD flags|CPUID level 0x80000001 (ecx) ====
 +^ Flag ^ Description ^
 +|lahf_lm|LAHF/​SAHF in long mode|
 +|cmp_legacy|If yes HyperThreading not valid|
 +|svm|"​Secure virtual machine":​ AMD-V (AMD’s virtualization extensions to the 64-bit x86 architecture,​ equivalent to Intel’s VMX, both also known as HVM in the Xen hypervisor.)|
 +|extapic|Extended APIC space|
 +|cr8_legacy|CR8 in 32-bit mode|
 +|abm|Advanced bit manipulation|
 +|sse4a|SSE-4A|
 +|misalignsse|Misaligned SSE mode|
 +|3dnowprefetch|3DNow prefetch instructions|
 +|osvw|OS Visible Workaround|
 +|ibs|Instruction Based Sampling|
 +|xop|extended AVX instructions|
 +|skinit|SKINIT/​STGI instructions|
 +|wdt|Watchdog timer|
 +|lwp|Light Weight Profiling|
 +|fma4|4 operands MAC instructions|
 +|tce|translation cache extension|
 +|nodeid_msr|NodeId MSR|
 +|tbm|trailing bit manipulations|
 +|topoext|topology extensions CPUID leafs|
 +|perfctr_core|core performance counter extensions|
 +
 +====== Transmeta-defined CPU features, CPUID level 0x80860001 ======
 +
 +|recovery|CPU in recovery mode|
 +|longrun|Longrun power control|
 +|lrti|LongRun table interface|
 +
 +====== Other features, Linux-defined mapping ======
 +
 +|cxmmx|Cyrix MMX extensions|
 +|k6_mtrr|AMD K6 nonstandard MTRRs|
 +|cyrix_arr|Cyrix ARRs (= MTRRs)|
 +|centaur_mcr|Centaur MCRs (= MTRRs)|
 +|constant_tsc|TSC ticks at a constant rate. On Intel P-4s, the TSC runs with constant frequency independent of cpu frequency when EST is used|
 +|up|smp kernel running on up|
 +|arch_perfmon|Intel Architectural PerfMon|
 +|pebs|Precise-Event Based Sampling|
 +|bts|Branch Trace Store|
 +|rep_good|rep microcode works well|
 +|nopl|The NOPL (0F 1F) instructions|
 +|xtopology|cpu topology enum extensions|
 +|tsc_reliable|TSC is known to be reliable|
 +|nonstop_tsc|TSC does not stop in C states|
 +|extd_apicid|has extended APICID (8 bits)|
 +|amd_dcm|multi-node processor|
 +|aperfmperf|APERFMPERF|
 +
 +====== Auxiliary flags defined by Linux ======
 +^ Flag ^ Description ^
 +|ida|Intel Dynamic Acceleration|
 +|arat|Always Running APIC Timer|
 +|cpb|AMD Core Performance Boost|
 +|epb|IA32_ENERGY_PERF_BIAS support|
 +|xsaveopt|Optimized Xsave|
 +|pln|Intel Power Limit Notification|
 +|pts|Intel Package Thermal Status|
 +|dts|Digital Thermal Sensor|
 +|hw_pstate|AMD HW-PState|
 +|Virtualization flags|Linux defined|
 +|tpr_shadow|Intel TPR Shadow (for virtualization)|
 +|vnmi|Intel Virtual NMI (non-maskable interrupts) (for virtualization)|
 +|flexpriority|Intel FlexPriority|
 +|ept|Intel Extended Page Table|
 +|vpid|Intel Virtual Processor ID (for virtualization)|
 +|npt|AMD Nested Page Table support (similar to ept on Intel)|
 +|lbrv|AMD LBR Virtualization support|
 +|svm_lock|AMD SVM locking MSR|
 +|nrip_save|AMD SVM next_rip save|
 +|tsc_scale|AMD TSC scaling support|
 +|vmcb_clean|AMD VMCB clean bits support|
 +|flushbyasid|AMD flush-by-ASID support|
 +|decodeassists|AMD Decode Assists support|
 +|pausefilter|AMD filtered pause intercept|
 +|pfthreshold|AMD pause filter threshold|
 +
 +====== Xen ======
 +
 +|hvm|Hardware support for virtual machines (Xen abbreviation for AMD SVM / Intel VMX)|
  

fuss/cpuflags.txt · Last modified: 2017/02/22 18:30 (external edit)

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