Intel-defined CPU features, CPUID level 0x00000001 (ecx)

Flag Description
pniPrescott New Instruction. This was the codename for SSE3 before it was released on the Intel Prescott processor (which was later added to the Pentium 4 family name).
pclmulqdqPCLMULQDQ instruction (carry-less multiplication — accelerator for GCM)
dtes6464-bit Debug Store
monitor/monMonitor/Mwait support (Intel SSE3 supplements)
ds_cplCPL Qual. Debug Store
vmxHardware virtualization: Intel VMX
smxSafer mode: TXT (TPM support)
eist/estEnhanced SpeedStep
tm2Thermal Monitor 2
sse3Streaming SIMD Extensions 3. (An additional 13 instructions) introduced with “Prescott” revision Intel Pentium 4 processors. AMD introduced SSE3 with the Athlon 64 “Venice” revision
ssse3Supplemental SSE-3
cidContext ID
fmaFused multiply-add
cx16CMPXCHG16B. CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for high resolution counters that could be updated by multiple processors (or cores). Without CMPXCHG16B the only way to perform such an operation is by using a critical section.
xtprSend Task Priority Messages. TPR register chipset update control messenger. Part of the APIC code.
pdcmPerformance Capabilities
pcidProcess Context Identifiers
dcaDirect Cache Access
sse4Streaming SIMD Extentions 4. Introduced with “Nehalem” processor in 2008. Also known as “Nehalem New Instructions (NNI)“
sse4_1Streaming SIMD Extentions 4.1
sse4_2Streaming SIMD Extentions 4.2
x2apicx2APIC
movbeMOVBE instruction
popcntPOPCNT instruction (Hamming weight, i.e. bit count)
tsc_deadline_timerTsc deadline timer
aesAES instructions: AES-NI
xsaveXSAVE/XRSTOR/XSETBV/XGETBV
avxAdvanced Vector Extensions
f16c16-bit fp conversions (CVT16)
rdrandThe RDRAND instruction (hardware random number generator)
hypervisorRunning on a hypervisor

VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001

rngRNG present (xstore)
rng_enRNG enabled
aceon-CPU crypto (xcrypt)
ace_enon-CPU crypto enabled
ace2Advanced Cryptography Engine v2
ace2_enACE v2 enabled
phePadLock Hash Engine
phe_enPHE enabled
pmmPadLock Montgomery Multiplier
pmm_enPMM enabled

Intel-defined CPU features, CPUID level 0x00000007:0 (ebx)

Flag Description
fsgsbase{RD/WR}{FS/GS}BASE instructions
bmi11st group bit manipulation extensions
hleHardware Lock Elision
avx2AVX2 instructions
smepSupervisor Mode Execution Protection
bmi22nd group bit manipulation extensions
ermsEnhanced REP MOVSB/STOSB
invpcidInvalidate Processor Context ID
rtmRestricted Transactional Memory

Intel-defined CPU features, CPUID level 0x00000001 (edx)

Flag Description
fpuOnboard FPU (floating point support)
vmeVirtual Mode Extensions (8086 mode)
deDebugging Extensions (CR4.DE)
psePage Size Extensions (4MB pages)
tscTime Stamp Counter (RDTSC)
msrModel-Specific Registers (RDMSR, WRMSR)
paePhysical Address Extensions (support for more than 4GB of RAM). PAE is the added ability of the IA32 processor to address more than 4 GB of physical memory using Intel’s 36bit page addresses instead of the standard 32bit page addresses to access a total of 64GB of RAM. Also supported by many AMD chips.
mceMachine Check Exception
cx8CMPXCHG8 instruction (64-bit compare-and-swap). Compare and exchange 8 bytes. Also known as F00F, which is an abbreviation of the hexadecimal encoding of an instruction that exhibits a design flaw in the majority of older Intel Pentium CPU.
apicOnboard APIC
sepSYSENTER/SYSEXIT
mtrrMemory Type Range Registers
pgePage Global Enable (global bit in PDEs and PTEs)
mcaMachine Check Architecture
cmovCMOV instructions (conditional move) (also FCMOV)
patPage Attribute Table
pse3636-bit PSEs (huge pages). Page Size Extensions 36. IA-32 supports two methods to access memory above 4 GB (32 bits), PSE and PAE. PSE is the older and far less used version.
pnProcessor serial number
clflushCLFLUSH instruction
dtsDebug Store (buffer for debugging and profiling instructions), can also mean Digital Thermal Sensor.
acpiACPI via MSR (temperature monitoring and clock speed modulation)
mmxext/mmxMultimedia Extensions
fxsrFXSAVE/FXRSTOR, CR4.OSFXSR
sseStreaming SIMD Extensions. Developed by Intel for its Pentium III but also implemented by AMD processors from Athlon XP onwards
sse2Streaming SIMD Extensions 2. (An additional 144 SIMDs.) Introduced by Intel Pentium 4, on AMD since Athlon 64
ssCPU self snoop
htt/htHyper-Threading or Hyper-Transport
tmAutomatic clock control (Thermal Monitor)
ia64IA-64 processor (not to be confused with x86-64 = amd64, indicated by lm)
pbePending Break Enable

AMD-defined CPU features, CPUID level 0x80000001

Flag Description
syscallSYSCALL/SYSRET (calls between the operating system and the hardware).
mpMP Capable.
nxNo eXecute, a flag that can be set on memory pages to disable execution of code in these pages.
mmxextAMD MMX extensions
fxsr_optFXSAVE/FXRSTOR optimizations
pdpe1gbGB pages
rdtscpRDTSCP
lmLong Mode (x86-64: amd64, also known as Intel 64, i.e. 64-bit capable)
3dnowextAMD 3DNow! extensions
3dnow3DNow! (AMD vector instructions, competing with Intel's SSE1)

More extended AMD flags|CPUID level 0x80000001 (ecx)

Flag Description
lahf_lmLAHF/SAHF in long mode
cmp_legacyIf yes HyperThreading not valid
svm“Secure virtual machine”: AMD-V (AMD’s virtualization extensions to the 64-bit x86 architecture, equivalent to Intel’s VMX, both also known as HVM in the Xen hypervisor.)
extapicExtended APIC space
cr8_legacyCR8 in 32-bit mode
abmAdvanced bit manipulation
sse4aSSE-4A
misalignsseMisaligned SSE mode
3dnowprefetch3DNow prefetch instructions
osvwOS Visible Workaround
ibsInstruction Based Sampling
xopextended AVX instructions
skinitSKINIT/STGI instructions
wdtWatchdog timer
lwpLight Weight Profiling
fma44 operands MAC instructions
tcetranslation cache extension
nodeid_msrNodeId MSR
tbmtrailing bit manipulations
topoexttopology extensions CPUID leafs
perfctr_corecore performance counter extensions

Transmeta-defined CPU features, CPUID level 0x80860001

recoveryCPU in recovery mode
longrunLongrun power control
lrtiLongRun table interface

Other features, Linux-defined mapping

cxmmxCyrix MMX extensions
k6_mtrrAMD K6 nonstandard MTRRs
cyrix_arrCyrix ARRs (= MTRRs)
centaur_mcrCentaur MCRs (= MTRRs)
constant_tscTSC ticks at a constant rate. On Intel P-4s, the TSC runs with constant frequency independent of cpu frequency when EST is used
upsmp kernel running on up
arch_perfmonIntel Architectural PerfMon
pebsPrecise-Event Based Sampling
btsBranch Trace Store
rep_goodrep microcode works well
noplThe NOPL (0F 1F) instructions
xtopologycpu topology enum extensions
tsc_reliableTSC is known to be reliable
nonstop_tscTSC does not stop in C states
extd_apicidhas extended APICID (8 bits)
amd_dcmmulti-node processor
aperfmperfAPERFMPERF

Auxiliary flags defined by Linux

Flag Description
idaIntel Dynamic Acceleration
aratAlways Running APIC Timer
cpbAMD Core Performance Boost
epbIA32_ENERGY_PERF_BIAS support
xsaveoptOptimized Xsave
plnIntel Power Limit Notification
ptsIntel Package Thermal Status
dtsDigital Thermal Sensor
hw_pstateAMD HW-PState
Virtualization flagsLinux defined
tpr_shadowIntel TPR Shadow (for virtualization)
vnmiIntel Virtual NMI (non-maskable interrupts) (for virtualization)
flexpriorityIntel FlexPriority
eptIntel Extended Page Table
vpidIntel Virtual Processor ID (for virtualization)
nptAMD Nested Page Table support (similar to ept on Intel)
lbrvAMD LBR Virtualization support
svm_lockAMD SVM locking MSR
nrip_saveAMD SVM next_rip save
tsc_scaleAMD TSC scaling support
vmcb_cleanAMD VMCB clean bits support
flushbyasidAMD flush-by-ASID support
decodeassistsAMD Decode Assists support
pausefilterAMD filtered pause intercept
pfthresholdAMD pause filter threshold

Xen

hvmHardware support for virtual machines (Xen abbreviation for AMD SVM / Intel VMX)

fuss/cpuflags.txt · Last modified: 2017/02/22 18:30 (external edit)

Access website using Tor


For the copyright, license, warranty and privacy terms for the usage of this website please see the license and privacy pages.